With recent memories, such as an SRAM (static random access memory), DRAM (dynamic random access memory), etc., advances in CMOS process technologies for SoC (system-on-chip) have lead to reduction of processing dimensions (scaling sizes) of integrated circuits and t his in turn has lead to realization of higher chip densities, lower chip costs, and increased memory capacity. Such reduction of scaling size causes increased variation of a threshold voltage of a transistor making up a memory cell of an SRAM, etc., lowering of read and write noise margins of the memory cell, destabilization of memory cell operation, and increase of bit error rate (BER). Also, soft errors due to cosmic rays are becoming non-negligible due to decreases of circuit operating voltage and noise margins.
FIG. 1 is a graph that shows SRAM operating limit voltages with respect to LSI manufacturing process nodes. The manner in which an operating margin between a standard operating voltage and an operating limit voltage decreases as the LSI manufacturing process node changes from 250 nm to 130 nm and then to 90 nm is shown. It is predicted that as the scaling size is reduced further and the LSI manufacturing process node reaches 65 nm, the relationship between the standard operating voltage and the operating limit voltage will become reversed to cause a sudden increase of bit error rate (BER).
As a measure for reducing the BER, there is a method of increasing a number of transistors in a memory cell. However, with the method of increasing the number of transistors, the memory cell becomes large in area overhead and there is a speed overhead due to an inability to perform differential reading. As another measure for reducing the BER, there is a method of performing voltage control of memory cell operations instead of current control. However, with the method of voltage control, a separate power supply, an additional circuit, etc., are separately required.
Meanwhile, the importance of reliability is dependent on application, and there are applications that require reliability and applications that do not require reliability. A cryptographic process is an example of an application that requires a high reliability. Oppositely, a screensaver process and a video or other moving image process are examples of applications that do not require a high reliability.
FIG. 2 is a schematic arrangement diagram of a conventional SRAM. With the conventional SRAM arrangement, all blocks (BLK 0 to BLK 5 in the figure) have the same reliability. A plurality of memory cells (MC) are present in each block, and one bit is allocated to one memory cell. An arrangement in which one bit is allocated to one memory cell shall hereinafter be defined as a 1-bit/1-cell mode. The reliability of one bit is highly dependent on variation due to process of the transistor that makes up the memory cell.
Also, when the manufacturing process node becomes thin due to scaling, the operating margin decreases, and the process variation comes to have a large influence on the reliability of one bit.
As examples of arts related to the conventional SRAM, Patent Document 1 and Patent Document 2 are known.    [Patent Document 1] JP-A-2005-25863    [Patent Document 2] JP-A-2003-132684